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[AMD][MI35X] Serve Qwen3.5 MXFP4-AttnFP8-V2 on sglang-rocm 20260913 - #2793

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amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len
Sep 14, 2026
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cquil11 merged 5 commits into
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amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len

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@yichiche

@yichiche yichiche commented Sep 1, 2026

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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=34758656500
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=34758656500

Summary

  • Switch qwen3.5-fp4-mi355x-sglang and qwen3.5-fp4-mi355x-sglang-mtp to amd/Qwen3.5-397B-A17B-MXFP4-AttnFP8-V2.
  • Bump both arms from lmsysorg/sglang-rocm:v0.5.18-rocm720-mi35x-20260829 to lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260913.
  • Keep the existing TP2 and TP4 search space ({ tp: 4, conc-start: 4, conc-end: 16 } and the MTP sibling). The previous TP4 drop on this PR is reverted so the new image plus AttnFP8-V2 checkpoint can be measured on both bands.

Details

MXFP4-AttnFP8-V2 keeps routed experts in MXFP4, quantizes the shared expert into the fused MoE kernel, and runs attention in FP8. It replaces amd/Qwen3.5-397B-A17B-MXFP4 as the MI355X SGLang fixed-seq-len checkpoint.

Launch scripts, isl/osl, and the atom / AgentX / disagg fp4 arms are unchanged. TP4 is left in the matrix so CI can show whether v0.5.19-rocm720-mi35x-20260913 still hits the old aiter gemm_a8w8_bpreshuffle N=32 hole.

Test plan

  • full-sweep-fail-fast for qwen3.5-fp4-mi355x-sglang and qwen3.5-fp4-mi355x-sglang-mtp passes on TP2 and TP4.

Note

Low Risk
Benchmark-only config and changelog updates; no application code or auth/data paths touched.

Overview
Updates the MI355X SGLang fixed-seq-len benchmark arms qwen3.5-fp4-mi355x-sglang and qwen3.5-fp4-mi355x-sglang-mtp to use checkpoint amd/Qwen3.5-397B-A17B-MXFP4-AttnFP8-V2 instead of amd/Qwen3.5-397B-A17B-MXFP4, and bumps the container image from lmsysorg/sglang-rocm:v0.5.18-rocm720-mi35x-20260829 to v0.5.19-rocm720-mi35x-20260913.

Scenario geometry (8k/1k, TP2/TP4 search space, MTP on the -mtp key) is unchanged in the diff; other Qwen3.5 FP4 arms (atom, agentic, disagg) stay on the prior model/image. perf-changelog.yaml records the model and image change for both config keys.

Reviewed by Cursor Bugbot for commit d2d0fbd. Bugbot is set up for automated code reviews on this repo. Configure here.

@yichiche
yichiche requested a review from a team September 1, 2026 07:52
@yichiche
yichiche force-pushed the amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len branch from 7608647 to 2b79ee4 Compare September 1, 2026 07:52
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Thanks for the contribution! Please reach out to respective companies' CODEOWNER to fill in the latest PR_REVIEW_CHECKLIST.md before pinging core maintainer on Slack for review. In order for the signoff PR check bot to trigger, you must follow the PR_REVIEW_CHECKLIST.md template correctly, including the phrase As a PR reviewer and CODEOWNER, I have reviewed this and have.

For PR verification, add the full-sweep-fail-fast label (strongly recommended) to this PR — the benchmark sweep only runs on labeled PRs. Use full-sweep-enabled only if you need matrix jobs to keep running past a failure.

PR authors are responsible for ensuring that after merging, all GitHub Action jobs fully pass. A lot of the time, failures are just flakes and simply re-running the failed jobs will fix it. See GitHub's docs on re-running failed jobs


感谢你的贡献!请联系相应公司的 CODEOWNER 填写最新的 PR_REVIEW_CHECKLIST.md,然后再在 Slack 上联系核心维护者进行审阅。为了触发 signoff PR 检查机器人,你必须正确遵循 PR_REVIEW_CHECKLIST.md 模板,包括保留英文语句 As a PR reviewer and CODEOWNER, I have reviewed this and have

如需进行 PR 验证,请为此 PR 添加 full-sweep-fail-fast 标签(强烈推荐)— 基准测试 sweep 仅在带有标签的 PR 上运行。仅当需要矩阵任务在失败后继续运行时才使用 full-sweep-enabled

PR 作者有责任确保合并后所有 GitHub Action 任务完全通过。 很多时候失败只是偶发抖动(flake),重新运行失败的任务即可解决。参见 GitHub 关于重新运行失败任务的文档

@yichiche yichiche changed the title [AMD][MI35X] Serve Qwen3.5 MXFP4-AttnFP8-V2 on the MI355X SGLang fixed-seq-len arms [AMD][MI35X] Serve Qwen3.5 MXFP4-AttnFP8-V2 on the MI355X SGLang Sep 1, 2026
Comment thread perf-changelog.yaml Outdated
description:
- "Serve amd/Qwen3.5-397B-A17B-MXFP4-AttnFP8-V2 instead of amd/Qwen3.5-397B-A17B-MXFP4, the newer AMD checkpoint that keeps MXFP4 MoE weights, quantizes the shared expert into the fused MoE kernel, and runs attention in FP8"
- "Add SGLANG_USE_AITER_FP8_PER_TOKEN=1 to benchmarks/single_node/fixed_seq_len/qwen3.5_fp4_mi355x.sh and qwen3.5_fp4_mi355x_mtp.sh so the FP8 attention weights take the per-channel/per-token aiter GEMM path published with the checkpoint instead of the per-tensor fallback"
pr-link: PR_LINK_PLACEHOLDER

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🔴 New changelog entry's pr-link is the literal placeholder string "PR_LINK_PLACEHOLDER" instead of a real PR URL, unlike every other entry in this append-only file. Fix: replace with the actual GitHub PR URL before merge; any tooling that parses pr-link (e.g. to build changelog links) will get a broken/non-URL value otherwise.

Extended reasoning...

perf-changelog.yaml is append-only and each prior entry (e.g. line 6730's pr-link: https://github.com/.../pull/2634) holds a real URL. This new entry at the tail sets pr-link: PR_LINK_PLACEHOLDER, so any consumer of this file (changelog renderer, doc generator, or a human clicking through) that expects a valid URL for every entry will fail or produce a dead link for this record specifically.

Verification: normal. The new entry at perf-changelog.yaml:6742 sets pr-link: PR_LINK_PLACEHOLDER, an invalid value. This is stronger than the candidate frames it (not just a dead link): the repo's own changelog gate rejects it. In utils/validate_perf_changelog.py, accepted placeholders are only PR_LINK_PLACEHOLDERS = {"XXX", "https://github.com/SemiAnalysisAI/InferenceX/pull/XXX"} (lines 24-27), and…

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@yichiche
yichiche force-pushed the amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len branch 3 times, most recently from c5f3422 to 3d25de8 Compare September 2, 2026 06:15
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yichiche force-pushed the amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len branch from 3d25de8 to febaac4 Compare September 2, 2026 06:19
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@yichiche
yichiche force-pushed the amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len branch from febaac4 to 92ccd3b Compare September 4, 2026 16:28
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@yichiche yichiche changed the title [AMD][MI35X] Serve Qwen3.5 MXFP4-AttnFP8-V2 on the MI355X SGLang [AMD][MI35X] Serve Qwen3.5 MXFP4-AttnFP8-V2 on sglang-rocm 20260912 Sep 13, 2026
@yichiche
yichiche force-pushed the amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len branch from 92ccd3b to d231e09 Compare September 13, 2026 12:48
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@yichiche yichiche changed the title [AMD][MI35X] Serve Qwen3.5 MXFP4-AttnFP8-V2 on sglang-rocm 20260912 [AMD][MI35X] Serve Qwen3.5 MXFP4-AttnFP8-V2 on sglang-rocm 20260913 Sep 13, 2026
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@1am9trash

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/reuse-sweep-run 34758656500

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As a PR reviewer and CODEOWNER, I have reviewed this and have:

  • Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
  • Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
  • Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link: https://inferencex.semianalysis.com/inference?unofficialRun=34758656500
  • Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Link: https://inferencex.semianalysis.com/evaluation?unofficialRun=34758656500
  • Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
  • For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
  • Verified against the current MODELS.md that this PR does not submit a deprecated model, scenario, or model-scenario combination.
  • Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
  • If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
  • If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
  • Verified that every single-node vLLM/SGLang recipe in this PR is documented in the official vLLM recipes and/or the SGLang cookbook:
    • I linked the corresponding upstream PR in the vLLM recipe repo or SGLang repo and verified that it is MERGED before this InferenceX PR merges. An opened, draft, or closed-without-merge upstream PR does not satisfy this requirement. If the matching recipe was already published, I linked the published recipe/cookbook page in the additional detail section below.
  • Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/<PR_NUMBER>.md — named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section.
  • If this PR uses append-only: true, verified that it only adds generated points or recipe variants inside a selected existing config/scenario and existing same-image visual curve: every previously generated point remains present with the same recipe, no prior point is removed or rerun, and every benchmark-affecting change in the complete diff can affect only the corresponding newly appended points (never an existing point), regardless of which file contains it.
  • If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

Additional detail section:

Signed: @1am9trash

@Klaud-Cold

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✅✅✅ Verdict: PASS ✅✅✅

✅ Check 0 (CODEOWNER): PASS — @1am9trash is a listed owner of configs/amd-master.yaml; perf-changelog.yaml is catch-all only.
✅ Check 1 (Sweep on in-PR commit): PASS — commit 4796505 (still in this PR) has all single-node 8k1k / (TP2 + TP4, both arms) and 4 eval / check-runs success in run 34758656500.
✅ Check 2 (Evals pass): PASS — gsm8k em_strict 0.967–0.970 across 4 TP2 configs (bar for qwen3.5: 0.94), run on amd/Qwen3.5-397B-A17B-MXFP4-AttnFP8-V2 with lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260913, matching this PR's config.
✅ Check 3 (Recipe linked/merged/complete): PASS — sgl-project/sglang#39358 is MERGED (2026-09-14T04:46Z) and the published cookbook now serves amd/Qwen3.5-397B-A17B-MXFP4-AttnFP8-V2 on MI355X. MAJOR args match: TP2/TP4, --attention-backend aiter, --page-size 16, --kv-cache-dtype fp8_e4m3, --disable-radix-cache, MTP as NEXTN(= EAGLE alias) with 3 steps / topk 1 / 4 draft tokens, and the AITER/FlyDSL/Mamba-SSM env. Informational only: scripts use ROCM_QUICK_REDUCE_QUANTIZATION=INT8 vs recipe INT4 (more conservative all-reduce precision), and --max-running-requests $CONC vs recipe's fixed 128 under MTP.
✅ Check 4 (Reuse command posted): PASS — /reuse-sweep-run 34758656500 posted by 1am9trash (COLLABORATOR).
✅ Check 5 (Latest checklist template): PASS — every current template item is present and checked.
✅ Check 6 (Upstream image / engine-first): PASS — both entries are framework: sglang on lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260913; ordering rule not applicable to an SGLang submission.
✅ Check 7 (Deprecated models/scenarios): PASS — qwen3.5 fp4 Single-turn 8k1k is active per MODELS.md as of 2026-09-14.
✅ Check 8 (Architecture hacks): PASS — no --hf-overrides or override knobs; the checkpoint swap lowers attention precision without removing FLOPs, and evals pass.
✅ Check 9 (Spec-decode chat template): PASS — qwen3.5_fp4_mi355x_mtp.sh benchmarks with --use-chat-template.
✅ Check 10 (Engine patches): PASS — no patch files, heredoc rewrites, or engine wheel installs; benchmark scripts are unchanged by this PR.
➖ Check 11 (Agentic spec-decode golden AL): N/A — fixed-seq-len arms only; no agentic spec-decode change.
➖ Check 12 (Append-only): N/A — the new perf-changelog.yaml entry has no append-only: true.

@cquil11
cquil11 merged commit 59dfae0 into main Sep 14, 2026
30 checks passed
@cquil11
cquil11 deleted the amd/qwen3.5-mxfp4-attnfp8-v2-mi355x-fixed-seq-len branch September 14, 2026 17:15
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